1. Field of the Invention
The present invention relates to timing circuits, systems, and control methods. In more specific applications, the invention relates to timing adjustment circuits for controlling logic races.
2. Description of the Related Art
Microprocessor architectures are continually evolving to improve and extend the capabilities of personal computers. Execution speed, power consumption, and circuit size are aspects of microprocessors and microprocessor performance that are constantly addressed by processor architects and designers in the ongoing quest for an improved product. Execution speed not only depends on the clock rate of a processor, but also upon the speed of interfaces such as cache memories and buses that supply instructions and data for execution by a processor core. The execution speed of microprocessors is heavily analyzed and compared using standard benchmark tests for judging the performance of competing entries into the microprocessor market.
Logic races are conditions that occur in a situation in which logic gates are enabled by signals received from a clocked device. If a data signal that is synchronized by a clock is delayed with respect to the clock, then incorrect data is propagated in a synchronous system.
One example of a circuit that may be affected by logic races is a self-timed regenerative sense amplifier in a memory circuit such as a cache. A memory array is activated by a signal on a word line in a parallel address path. A clock signal is buffered to strobe the self-timed, regenerative sense amplifier. A problem that may arise is that the sense amplifier may be strobed too early, before a sufficient signal is developed on the bit lines, so that an incorrect value is sensed by the sense amplifiers. Since the sense amplifier is regenerative, recovery of the error does not occur.
In manufactured integrated circuits, a sense amplifier has a specific offset voltage that varies as a function of sense amplifier design, layout, process, matching of devices in the process, and the like. Therefore, the offset voltage of the sense amplifiers on a integrated circuit varies within some range. During the design of the integrated circuit, the ultimate matching of devices, the performance resulting from the layout, and other design effects are difficult to anticipate. Therefore, a designer has difficulty ascertaining how aggressively to set device dimensions that determine the timing characteristics in a synchronous system. If the timing is set too aggressively, logical races may result since logic race conditions are generally avoided by delaying clock signals with respect to data. However, if the timing is not sufficiently aggressive, the integrated circuit speed performance is compromised.
What are needed in microprocessors are circuits and operating methods for attaining a fast speed performance while avoid logic races.